adms is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Based on transformations specified in xml language adms transforms Verilog-AMS code into other target languages.
Typical run:
admsXml <vafile> -e <controlfile1>.xml -e <controlfile2>.xml -e ...
admsXml mysource.va -e myxml.xml
The internal data structure of adms is auto-generated from file adms.xml . This file is very important. The rules used to build a control file are based on its contents. More in section Documentations.